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A Parallel Rendering Algorithm for MIMD ArchitecturesApplications such as animation and scientific visualization demand high performance rendering of complex three dimensional scenes. To deliver the necessary rendering rates, highly parallel hardware architectures are required. The challenge is then to design algorithms and software which effectively use the hardware parallelism. A rendering algorithm targeted to distributed memory MIMD architectures is described. For maximum performance, the algorithm exploits both object-level and pixel-level parallelism. The behavior of the algorithm is examined both analytically and experimentally. Its performance for large numbers of processors is found to be limited primarily by communication overheads. An experimental implementation for the Intel iPSC/860 shows increasing performance from 1 to 128 processors across a wide range of scene complexities. It is shown that minimal modifications to the algorithm will adapt it for use on shared memory architectures as well.
Document ID
19910017453
Acquisition Source
Legacy CDMS
Document Type
Contractor Report (CR)
Authors
Crockett, Thomas W.
(Institute for Computer Applications in Science and Engineering Hampton, VA., United States)
Orloff, Tobias
(Great Northwestern Graphics Minneapolis, MN., United States)
Date Acquired
September 6, 2013
Publication Date
June 1, 1991
Subject Category
Computer Programming And Software
Report/Patent Number
NAS 1.26:187571
ICASE-91-3
NASA-CR-187571
AD-A237743
Accession Number
91N26767
Funding Number(s)
CONTRACT_GRANT: NAS1-18605
PROJECT: RTOP 505-90-52-01
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
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